general description the MAX4684/max4685 low on-resistance (r on ), low- voltage, dual single-pole/double-throw (spdt) analog switches operate from a single +1.8v to +5.5v supply. the MAX4684 features a 0.5 (max) r on for its nc switch and a 0.8 (max) r on for its no switch at a +2.7v supply. the max4685 features a 0.8 max on- resistance for both no and nc switches at a +2.7v supply. both parts feature break-before-make switching action (2ns) with t on = 50ns and t off = 40ns at +3v. the digi- tal logic inputs are 1.8v logic-compatible with a +2.7v to +3.3v supply. the MAX4684/max4685 are packaged in the chipscale package (ucsp) , significantly reducing the required pc board area. the chip occupies only a 2.0mm ? 1.50mm area. the 4 ? 3 array of solder bumps are spaced with a 0.5mm bump pitch. ________________________applications speaker headset switching mp3 players power routing battery-operated equipment relay replacement audio and video signal routing communications circuits pcmcia cards cellular phones modems features ? 12-bump, 0.5mm-pitch ucsp ? nc switch r on 0.5 max (+2.7v supply) (MAX4684) 0.8 max (+2.7v supply) (max4685) ? no switch r on 0.8 max (+2.7v supply) ? r on match between channels 0.06 (max) ? r on flatness over signal range 0.15 (max) ? +1.8v to +5.5v single-supply operation ? rail-to-rail signal handling ? 1.8v logic compatibility ? low crosstalk: -68db (100khz) ? high off-isolation: -64db (100khz) ? thd: 0.03% ? 50na (max) supply current ? low leakage currents 1na (max) at t a = +25? MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp ________________________________________________________________ maxim integrated products 1 19-1977; rev 4; 1/09 com2 com1 no2 no1 nc2 in2 in1 nc1 gnd v+ top view in_ 0 1 no_ MAX4684/max4685 off on nc_ on switches shown for logic "0" input off ucsp MAX4684/max4685 MAX4684/max4685 nc2 in1 gnd nc1 2 3 9 8 com2 in2 com1 no1 1 10 no2 v+ 4 5 7 6 max c1 c2 c3 c4 b4 a4 a3 a2 a1 b1 pin configurations/functional diagrams/truth table ucsp is a trademark of maxim integrated products, inc. ?ax is a registered trademark of maxim integrated products, inc. for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. continued at end of data sheet. ordering information + denotes a lead(pb)-free/rohs-compliant package. note: requires special solder temperature profile described in the absolute maximum ratings section. * ucsp reliability is integrally linked to the user? assembly methods, circuit board material, and environment. refer to the ucsp reliability notice in the ucsp reliability section of this data sheet for more information. ** ep = exposed pad t = tape and reel. part temp range pin /b u m p- package top mark m a x4 6 8 4 e bc + t -40 c to +85 c 12 ucsp* aaf m ax 4684e tb+ t -40 c to +85 c 10 td fn - e p ** aag m ax 4684e u b+ t -40 c to +85 c 10 ?ax m a x4 6 8 5 e bc + t -40 c to +85 c 12 ucsp* aag m ax 4685e tb+ t -40 c to +85 c 10 td fn - e p ** aah m ax 4685e u b+ t -40 c to +85 c 10 ?ax
MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd) v+, in_......................................................................-0.3v to +6v com_, no_, nc_ (note1) ........................... -0.3v to (v+ + 0.3v) continuous current no_, nc_, com_ .......................... ?00ma peak current no_, nc_, com_ (pulsed at 1ms, 50% duty cycle).................................?00ma peak current no_, nc_, com_ (pulsed at 1ms, 10% duty cycle).................................?00ma continuous power dissipation (t a = +70?) 10-pin tdfn (derate 18.5m w/? above +7 0?)........1482mw 12-bump ucsp (derate 11.4mw/? above +70?) ...909mw 10-pin ?ax (derate 5.6mw/? above +70?) ..........444mw operating temperature ranges..........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? bump temperature (soldering) (note 2) infared (15s)................................................................+220? vapor phase (60s) ......................................................+215? note 1: signals on no_, nc_, and com_ exceeding v+ or gnd are clamped by internal diodes. limit forward-diode current to maximum current rating. note 2: this device is constructed using a unique set of packaging techniques that impose a limit on the thermal profile the device can be exposed to during board level solder attach and rework. this limit permits only the use of the solder profiles recom- mended in the industry-standard specification, jedec 020a, paragraph 7.6, table 3 for ir/vpr and convection reflow. pre- heating is required. hand or wave soldering is not allowed. parameter symbol conditions t a min typ max units analog switch analog signal range v no _, v nc _, v com _ e0 v+v +25 c 0.3 0.5 MAX4684 e 0.5 +25 c0.450.8 nc_ on-resistance (note 4) r on(nc) v + = 2.7v ; i c om _ = 100ma; v nc _ = 0 to v+ max4685 e 0.8 c0.450.8 no_ on-resistance (note 4) r on(no) v+ = 2.7v; i com _ = 100ma; v no _ = 0 to v+ e 0.8 c0.06 on-resistance match between channels (notes 4, 5) r on v+ = 2.7v; i com _ = 100ma; v no _ or v nc _ = 1.5v e 0.06 no_ on-resistance flatness (note 6) r flat (no) v+ = 2.7v; i com = 100ma; v no _ = 0 to v+ e 0.35 c -1 1 no_ or nc_ off- leakage current (note 7) i no _(off) or i nc _(off) v+ = 3.3v; v no _ or v nc _ = 3v, 0.3v; v com _ = 0.3v, 3v e -10 10 na +25 c -2 2 com_ on-leakage current (note 7) i com _(on) v + = 3.3v ; v n o _ or v n c _ = 3v , 0.3v , or unconnected ; v c om _ = 3v , 0.3v , or unconnected e -20 20 na dynamic characteristics +25 c 30 50 turn-on time t on v+ = 2.7v, v no _ or v nc _ = 1.5v; r l = 50 ; c l = 35pf; figure 2 e60 ns electrical characteristics?3v supply (v+ = +2.7v to +3.3v, v ih = +1.4v, v il = +0.5v, t a = t min to t max , unless otherwise noted. typical values are at +3v and +25?.) (notes 3, 9, 10)
MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp _______________________________________________________________________________________ 3 electrical characteristics?3v supply (continued) (v+ = +2.7v to +3.3v, v ih = +1.4v, v il = +0.5v, t a = t min to t max , unless otherwise noted. typical values are at +3v and +25?.) (notes 3, 9, 10) parameter symbol conditions t a min typ max units +25 c 25 30 turn-off time t off v+ = 2.7v, v no _ or v nc _ = 1.5v; r l = 50 ; c l = 35pf; figure 2 e40 ns break-before-make delay t bbm v+ = 2.7v, v no _, or v nc _ = 1.5v; r l = 50 ; c l = 35pf; figure 3 e 2 15 ns charge injection q com_ = 0; r s = 0; c l = 1nf; figure 4 +25 c 200 pc off-isolation (note 8) v iso c l = 5pf; r l = 50 ; f = 100khz; v com _ = 1v rms ; figure 5 +25 c -64 db crosstalk v ct c l = 5pf; r l = 50 ; f = 100khz; v com _ = 1v rms ; figure 5 +25 c -68 db total harmonic distortion thd r l = 600 , in_ = 2vp-p, f = 20hz to 20khz +25 c0.03 % nc_ off-capacitance c nc_ ( off ) f = 1mhz; figure 6 +25 c 84 pf no_ off-capacitance c no_(off) f = 1mhz; figure 6 +25 c 37 pf nc_ on-capacitance c nc_(on) f = 1mhz; figure 6 +25 c 190 pf no_ on-capacitance c no_(on) f = 1mhz; figure 6 +25 c 150 pf digital i/o input logic high v ih e1.4 v input logic low v il e 0.5 v in_ input leakage current i in _v in _ = 0 or v+ e -1 1 ? power supply power-supply range v+ e 1.8 5.5 v +25 c -50 0.04 50 s up p l y c ur r ent ( n ote 4) i+ v+ = 5.5v; v in _ = 0 or v+ e -200 200 na note 3: the algebraic convention used in this data sheet is where the most negative value is a minimum and the most positive value a maximum. note 4: guaranteed by design. note 5: r on = r on(max) - r on(min) , between nc1 and nc2 or between no1 and no2. note 6: flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the specified analog signal ranges. note 7: leakage parameters are 100% tested at t a = +85?, and guaranteed by correlation over rated temperature range. note 8: off-isolation = 20log 10 (v com / v no ), v com = output, v no = input to off switch. note 9: ucsp and tdfn parts are 100% tested at +25? only and guaranteed by design and correlation at the full hot-rated temperature. note 10: -40? specifications are guaranteed by design.
MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp 4 _______________________________________________________________________________________ typical operating characteristics (t a = +25?, unless otherwise noted.) 0 0.4 0.2 1.0 0.8 0.6 1.6 1.4 1.2 1.8 02 1 345 MAX4684 nc on-resistance vs. com voltage MAX4684/5 toc01 v com (v) r on ( ) v+ = +3.0v v+ = +5.0v v+ = +1.8v v+ = +2.0v v+ = +2.3v v+ = +2.5v no on-resistance vs. com voltage 0 0.5 1.5 1.0 2.0 2.5 02 1345 r on ( ) MAX4684/5 toc03 v com (v) v+ = +5.0v v+ = +1.8v v+ = +2.0v v+ = +2.3v v+ = +2.5v v+ = +3.0v max4685 nc on-resistance vs. com voltage 0 0.2 0.4 0.6 0.8 1.2 1.4 1.8 1.0 1.6 2.0 02 1345 r on ( ) MAX4684/5 toc02 v com (v) v+ = +5.0v v+ = +2.3v v+ = +3.0v v+ = +1.8v v+ = +2.0v v+ = +2.5v 0.10 0.12 0.14 0.16 0.20 0.18 0.22 0.24 0.26 0.28 02 1345 MAX4684/5 toc04 MAX4684 nc on-resistance vs. com voltage v com (v) r on ( ) t a = +85 c v+ = +5v t a = -40 c t a = +25 c 0.10 0.15 0.20 0.25 0.30 0.35 0.40 012345 MAX4684/5 toc06 no on-resistance vs. com voltage v com (v) r on ( ) t a = +85 c v+ = +5v t a = -40 c t a = +25 c 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 012345 MAX4684/5 toc05 max4685 nc on-resistance vs. com voltage v com (v) r on ( ) v+ = +5v t a = +25 c t a = -40 c t a = +85 c 01.01.5 0.5 2.0 2.5 3.0 0.10 0.15 0.20 0.25 0.30 0.35 MAX4684/5 toc07 MAX4684 nc on-resistance vs. com voltage v com (v) r on ( ) v+ = +3v t a = +85 c t a = -40 c t a = +25 c 0.15 0.10 0.20 0.25 0.30 0.35 0.40 0.45 0.50 01.0 0.5 1.5 2.0 2.5 3.0 MAX4684/5 toc09 no on-resistance vs. com voltage v com (v) r on ( ) v+ = +3v t a = +85 c t a = +25 c t a = -40 c 0.15 0.10 0.20 0.25 0.30 0.35 0.40 0.45 0.50 01.0 0.5 1.5 2.0 2.5 3.0 MAX4684/5 toc08 max4685 nc on-resistance vs. com voltage v com (v) r on ( ) v+ = +3v t a = +85 c t a = +25 c t a = -40 c
MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp _______________________________________________________________________________________ 5 0 20 60 40 80 100 02 1 3456 supply current vs. supply voltage MAX4684/5 toc10 v supply (v) supply current (pa) 0 20 10 40 30 50 60 70 80 1.8 2.8 3.3 2.3 3.8 4.3 4.8 5.3 MAX4684/5 toc11 v supply (v) t on /t off (ns) turn-on/turn-0ff times vs. supply voltage t on t off 0 15 10 5 20 25 30 35 40 45 50 -40 10 -15 356085 MAX4684/5 toc12 turn-on/turn-0ff times vs. temperature v+ = +3v t on /t off (ns) temperature ( c) t on t off 2.0 1.5 1.0 0.5 0 03 1 2 456 logic threshold voltage vs. supply voltage MAX4684/5 toc13 logic threshold voltage (v) v supply (v) v in rising v in falling -500 -400 -300 -200 -100 0 100 200 300 02 1 3456 charge injection vs. com voltage MAX4684/5 toc14 q (pc) v com (v) -40 10 -15 35 60 85 MAX4684/5 toc15 temperature ( c) on/off-leakage current (pa) 1 10 100 1000 MAX4684 on/off-leakage current vs. temperature i com(on) i com(off) -40 10 -15 35 60 85 MAX4684/5 toc16 temperature ( c) on/off-leakage current (pa) 1 10 100 1000 max4685 on/off-leakage current vs. temperature i com(on) i com(off) frequency response (max) frequency (mhz) 0.001 1 10 100 0.01 0.1 loss (db) -120 -100 -80 -20 -40 -60 0 MAX4684/85 toc17 on- response off- isolation crosstalk 10 100 1k 10k 100k total harmonic distortion plus noise vs. frequency MAX4684/5 toc18 frequency (hz) thd + n (%) 0.01 0.1 typical operating characteristics (continued) (t a = +25?, unless otherwise noted.)
MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp detailed description the MAX4684/max4685 are low on-resistance, low- voltage, dual spdt analog switches that operate from a +1.8v to +5.5v supply. the devices are fully specified for nominal 3v applications. the MAX4684/max4685 have break-before-make switching and fast switching speeds (t on = 50ns max, t off = 40ns max). the MAX4684 offers asymmetrical normally closed (nc) and normally open (no) r on for applications that require asymmetrical loads (examples include speaker headsets and internal speakers). the part features a 0.5 max r on for its nc switch and a 0.8 max ron for its no switch at the 2.7v supply. the max4685 fea- tures a 0.8 max on-resistance for both no and nc switches at the +2.7v supply. applications information digital control inputs the MAX4684/max4685 logic inputs accept up to +5.5v regardless of supply voltage. for example, with a +3.3v supply, in_ may be driven low to gnd and high to 5.5v. driving in_ rail-to-rail minimizes power con- sumption. logic levels for a +1.8v supply are 0.5v (low) and 1.4v (high). analog signal levels analog signals that range over the entire supply voltage (v+ to gnd) are passed with very little change in on- resistance (see typical operating characteristics ). the switches are bidirectional, so the no_, nc_, and com_ pins can be either inputs or outputs. power-supply sequencing and overvoltage protection caution: do not exceed the absolute maximum rat- ings because stresses beyond the listed ratings may cause permanent damage to devices. proper power-supply sequencing is recommended for all cmos devices. always apply v+ before applying analog signals, especially if the analog signal is not current limited. if this sequencing is not possible, and if the analog inputs are not current limited to <20ma, add a small signal diode (d1) as shown in figure 1. adding a protection diode reduces the analog range to a diode drop (about 0.7v) below v+ (for d1). r on increases slightly at low supply voltages. maximum supply volt- age (v+) must not exceed +6v. protection diode d1 also protects against some overvoltage situations. no damage will result on figure 1? circuit if the supply voltage is below the absolute maximum rating applied to an analog signal pin. positive supply com no d1 gnd v g v+ MAX4684 max4685 figure 1. overvoltage protection using two external blocking diodes pin name ucsp ?ax/tdfn function nc_ a1, c1 5, 7 analog switch?ormally closed terminal in_ a2, c2 4, 8 digital control input com_ a3, c3 3, 9 analog switch?ommon terminal no_ a4, c4 2, 10 analog switch?ormally open terminal v+ b4 1 positive supply voltage input gnd b1 6 ground ep exposed pad. connect ep to gnd (for tdfn only.) pin description 6 _______________________________________________________________________________________
ucsp package consideration for general ucsp package information and pc layout considerations, please refer to the maxim application note (wafer-level ultra-chip-board-scale package). ucsp reliability the chip-scale package (ucsp) represents a unique packaging form factor that may not perform equally to a packaged product through traditional mechanical relia- bility tests. ucsp reliability is integrally linked to the user? assembly methods, circuit board material, and usage environment. the user should closely review these areas when considering use of a ucsp package. performance through operating life test and moisture resistance remains uncompromised as it is primarily determined by the wafer-fabrication process. mechanical stress performance is a greater considera- tion for a ucsp package. ucsps are attached through direct solder contact to the user? pc board, foregoing the inherent stress relief of a packaged product lead frame. solder joint contact integrity must be consid- ered. information on maxim? qualification plan, test data, and recommendations are detailed in the ucsp application note, which can be found on maxim? web- site at www.maxim-ic.com. chip information process: bicmos MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp _______________________________________________________________________________________ 7 t r < 5ns t f < 5ns 50% v il logic input r l 50 com_ gnd in_ c l includes fixture and stray capacitance. v out = v n_ ( r l ) r l + r on v in_ v ih t off 0 no_ or nc 0.9 x v 0ut 0.9 x v out t on v out switch output logic input logic input waveforms inverted for switches that have the opposite logic sense. v+ c l 35pf v+ v out MAX4684 max4685 figure 2. switching time test circuits/timing diagrams 50% v ih v il logic input v out 0.9 x v out t d logic input r l 50 gnd c l includes fixture and stray capacitance. no_ in_ nc_ v out v+ v+ c l 35pf v n_ com_ MAX4684 max4685 figure 3. break-before-make interval
MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp 8 _______________________________________________________________________________________ v gen gnd com_ c l v out v+ v out in off on off v out q = ( v out )(c l ) nc_ in depends on switch configuration; input polarity determined by sense of switch. off on off in v il to v ih v+ r gen in_ MAX4684 max4685 or no_ figure 4. charge injection measurements are standardized against shorts at ic terminals. off-isolation is measured between com_ and "off" no_ or nc_ terminal on each switch. on-loss is measured between com_ and "on" no_ or nc_ terminal on each switch. crosstalk is measured from one channel to all other channels. signal direction through switch is reversed; worst values are recorded. +5v v out v+ in_ nc_ com no v in MAX4684 max4685 off-isolation = 20log v out v in on-loss = 20log v out v in crosstalk = 20log v out v in network analyzer 50 50 50 50 meas ref 10nf 0v or v+ 50 gnd figure 5. on-loss, off-isolation, and crosstalk capacitance meter nc_ or no_ com_ gnd in v il or v ih 10nf v+ f = 1mhz v+ MAX4684 max4685 figure 6. channel off/on-capacitance test circuits/timing diagrams (continued) top view nc2 in1 gnd nc1 com2 in2 com1 no1 no2 v+ 3mm ? 3mm tdfn 9 8 10 7 6 *connect ep to gnd. 2 3 1 4 5 *ep MAX4684/max4685 pin configurations (continued)
MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp _______________________________________________________________________________________ 9 package type package code document no. 12 ucsp b12-4 21-0104 10 tdfn-ep t1033-1 21-0137 10 ?ax u10-2 21-0061 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages .
MAX4684/max4685 0.5 /0.8 low-voltage, dual spdt analog switches in ucsp maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products is a registered trademark of maxim integrated products. revision history revision number revision date description pages changes 3 2/03 added tdfn packaging, noted parts are now ucsp qualified 4 1/09 added lead-free packaging and exposed pad note 1, 2, 6?
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